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SERIAL CONTROL MODULE: SPI
SPI clock generation
436 Hardware Reference NS9215
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SPI clock generation
The reference clock for the SPI module is the system PLL output. This clock is a
nominal 300 MHz.
In SPI master mode, the clock is divided down to produce the required data
rate.
In SPI slave mode, the divided down clock recovers the input SPI clock.
Clock generation
samples
SPI clock generation is specified using the Clock Generation register. These are
some examples of clock generation:
In SPI master
mode
In SPI master mode, the value programmed in the DIVISOR field must always be
rounded up to the next whole integer. For example, if the required data rate is 14
Mbps, the calculation is (300 / 14) or 21.43.
The value programmed in the DIVISOR field would be 0x016.
The actual data rate would be 13.64 Mbps.
The general equation is:
DIVISOR = round Up (PLL output / interface data rate)
In SPI slave mode In SPI slave mode, the value programmed in the DIVISOR field should always be 0x006.
The SPI slave mode data rate is determined by the frequency of the input clock
provided by the external SPI master.
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System boot-over-SPI operation
The NET+SPI ASIC boots from an external, non-volatile, serial memory device. The
device can be either a serial EEPROM or a serial Flash. In either case, the device
must support a four-wire, mode0-compatible SPI interface.
The boot-over-SPI hardware interfaces to devices requiring an 8-bit address, 16-bit
address, or 24-bit address. The address width is indicated by strapping pins
boot_mode[1:0].
Interface Type Data rate DIVISOR
Master 33 Mbps 0x009
Master 20 Mbps 0x00F
Master 5 Mbps 0x03C
Master 500 Kbps 0x258
Slave all 0x006