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MEMORY CONTROLLER
Dynamic Memory Data-in to Active Command Time register
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Register
Register bit
assignment
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Dynamic Memory Data-in to Active Command Time register
Address: A070 0040
The Dynamic Memory Data-in to Active Command Time register allows you to
program the data-in to active command time, t
DAL
. It is recommended that this
register be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode. This value normally is found in SDRAM data sheets as t
DAL
or t
APW
.
Note:
The Dynamic Memory Data-in Active Command Time register is used for all
four dynamic memory chip selects. The worst case value for all chip selects
must be programmed.
Register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved APR
Bits Access Mnemonic Description
D31:04 N/A Reserved N/A (do not modify)
D03:00 R/W APR Last-data-out to active command time (t
APR
)
0x0–0xE
n+1 clock cycles, where the delay is in clk_out cycles.
0xF
16 clock cycles (reset value on reset_n)
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved DAL