Filter
Top Products
ETHERNET COMMUNICATION MODULE
Ethernet Transmit Status register
284 Hardware Reference NS9215
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Transmit Status register
Address: A060 0018
The Ethernet Status register contains the status for the last transmit frame. The
TXDONE bit in the Ethernet Interrupt Status register (see page 317) is set upon
completion of a transmit frame and the Ethernet Transmit Status register is loaded
at the same time. Bits [15:0] are also loaded into the Status field of the last
transmit buffer descriptor for the frame.
Register
Reserved
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
RX
INIT
Reserved
Bits Access Mnemonic Reset Description
D31:21 N/A Reserved N/A N/A
D20 R/C RXINIT 0x0 RX initialization complete
Set when the
RX_RD logic has completed the
initialization of the local buffer descriptor registers
requested when ERXINIT in Ethernet General
Control Register #1 is set. The delay from ERXINIT
set to RXINIT set is less than five microseconds.
D19:00 N/A Reserved N/A N/A
Reserved
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Not
used
TX
DEF
TX
CRC
Not
used
TXCOLC
TX
OK
TX
BR
TX
MC
TX
AL
TX
AED
TX
AEC
TX
AUR
TX
AJ