Filter
Top Products
MEMORY CONTROLLER
Static memory read: Timing and parameters
212 Hardware Reference NS9215
External memory
read transfer with
two output enable
delay states
This diagram shows an external memory read transfer with two output enable delay
states (
WA ITO EN= 2). Seven AHB cycles are required for the transfer, five for the
standard read and an additional two because of the output delay states added.
External memory
read transfers
with zero wait
states
This diagram shows external memory read transfers with zero wait states
(
WA IT RD= 0). These transfers can be non-sequential transfers or sequential transfers
of a specified burst length. Bursts of unspecified length are interpreted as INCR4
transfers. All transfers are treated as separate reads, so have the minimum of five
AHB cycles added.
WAITEN N/A
WAITTURN N/A
Timing parameter Value
Timing parameter Value
WAITRD 2
WAITOEN 2
WAITPAGE N/A
WAITWR N/A
WAITWEN N/A
WAITTURN N/A
A
D(A)
addr
data
cs[n]
st_oe_n
clk_out
B
D(B)
A 0
D(A)
clk_out
addr
data
cs[n]
st_oe_n