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SERIAL CONTROL MODULE: HDLC
HDLC Data Register 1
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HDLC Data Register 1
Address: 9002_9100
HDLC Data Register 1 reads data from the receive buffer and load data in the
transmit buffer. This register is for debug purposes only.
Register
Register bit
assignment
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HDLC Data Register 2
Address: 9002_9104
HDLC Data Register 2 writes the last byte of data of a frame after which the CRC
and closing flag are transmitted. This register is for debug purposes only.
D01 R/W1TC TX_IDLE 0 Transmit idle
Indicates that the transmitter has moved from the active
state to the idle state. The transmitter moves from the active
state to the idle state when the transmit FIFO is empty and
the transmitter is not actively shifting out data.
D00 R/W1TC RX_IDLE 0 Receive idle
Indicates that the receiver has moved from the active state
to the idle state. The receiver moves from the active state to
the idle state when a start bit has not been received after the
previous stop bit.
Bits Access Mnemonic Reset Description
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved HDATA
Reserved
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved 0 N/A
D07:00 R/W HDATA 0 Read Returns the contents of the receive buffer
Write Loads the transmit buffer with a byte of data