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ETHERNET COMMUNICATION MODULE
Statistics registers
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HT2 Address: A060 0508
Register bit assignment
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Statistics registers
Address: A060 0680 (base register)
The Statistics module has 39 counters and 4 support registers that count and save
Ethernet statistics. The Ethernet General Control Register #2 contains three
Statistics module configuration bits: AUTOZ, CLRCNT, and STEN. The counters
support a “clear on read” capability that is enabled when AUTOZ is set to 1.
Combined
transmit and
receive statistics
counters address
map
The combined transmit and receive statistics counters are incremented for each
good or bad frame, transmitted and received, that falls within the specified frame
length limits of the counter (for example, TR127 counts 65–127 byte frames). The
frame length excludes framing bits and includes the FCS (checksum) bytes. All
counters are 18 bits, with this bit configuration:
Bits Access Mnemonic Reset Description
D31:00 R/W HT2 0x00000000 CRC 63:32
HT2
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
HT2
D31:18 R Reserved
D17:00 R/W Reset = 0x00000 Count (R/W)
Address Register Transmit and receive counters R/W
A060_0680 TR64 Transmit & receive 64 Byte frame counter R/W
A060_0684 TR127 Transmit & receive 65 to 127 Byte frame counter R/W
A060_0688 TR255 Transmit & receive 128 to 255 Byte frame counter R/W
A060_068C TR511 Transmit & receive 256 to 511 Byte frame counter R/W
A060_0690 TR1K Transmit & receive 512 to 1023 Byte frame counter R/W