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EXTERNAL DMA
Peripheral DMA write access
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Peripheral DMA
single read access
Peripheral DMA
burst read access
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Peripheral DMA write access
The diagrams in this section describe how the DMA engine performs write accesses
of an external peripheral. The CLK signal shown is for reference, and its frequency
is equal to the speed grade of the part. For peripheral writes, the PDEN signal is an
AND function of the active status of
st_cs_n[n] and we_n. Write data into the
peripheral on the falling edge of the PDEN signal. Data and control signals are
always held after the falling edge of PDEN for one reference CLK cycle.
DATA VALID
PDEN
DQ
st_cs_n[n]
CLK
ADDR
Address Valid
st_oe_n
PDEN
DQ
st_cs_n[n]
CLK
DATA0 DATA1
ADDR0 ADDR1ADDR
st_oe_n