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WORKING WITH THE CPU
R7:Cache Operations register
94 Hardware Reference NS9215
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R7:Cache Operations register
Register R7 controls the caches and write buffer. The function of each cache
operation is selected by the
opcode_2 and CRm fields in the MCR instruction that
writes to CP15 R7. Writing other
opcode_2 or CRm values is UNPREDICTABLE.
Reading from R7 is UNPREDICTABLE, with the exception of the two test and clean
operations (see “Cache operation functions” on page 95 and “Test and clean
DCache instructions” on page 96).
Write instruction Use this instruction to write to the Cache Operations register:
MCR p15, opcode_1, Rd, CRn, CRm, opcode_2
Cache functions This table describes the cache functions provided by register R7.
Function Description
Invalidate cache Invalidates all cache data, including any dirty data.
Invalidate single entry using either index or
modified virtual address
Invalidates a single cache line, discarding any dirty data.
Clean single data entry using either index or
modified virtual address
Writes the specified DCache line to main memory if the
line is marked valid and dirty. The line is marked as not
dirty, and the valid bit is unchanged.
Clean and invalidate single data entry using
wither index or modified virtual address.
Writes the specified DCache line to main memory if the
line is marked valid and dirty. The line is marked not valid.
Test and clean DCache Tests a number of cache lines, and cleans one of them if
any are dirty. Returns the overall dirty state of the cache in
bit 30. (See “Test and clean DCache instructions” on
page 96).
Test, clean, and invalidate DCache Tests a number of cache lines, and cleans one of them if
any are dirty. When the entire cache has been tested and
cleaned, it is invalidated. (See “Test and clean DCache
instructions” on page 96).
Prefetch ICache line Performs an ICache lookup of the specified modified
virtual address. If the cache misses and the region is
cachable, a linefill is performed.