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SYSTEM CONTROL MODULE
Timer Master Control register
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Register bit
assignment
Bits Access Mnemonic Reset Description
D31:22 N/A Reserved N/A N/A
D21 R/W T9RSE 0x0 Timer 9 reload step enable
0 Reload Step register disabled
1 Reload Step register enabled
D20 R/W T9LSE 0x0 Timer 9 low step enable
0 Low Step register disabled
1 Low Step register enabled
D19 R/W T9HSE 0x0 Timer 9 high step enable
0 High Step register disabled
1 High Step register enabled
D18 R/W T8RSE 0x0 Timer 8 reload step enable
0 Reload Step register disabled
1 Reload Step register enabled
D17 R/W T8LSE 0x0 Timer 8 low step enable
0 Low Step register disabled
1 Low Step register enabled
D16 R/W T8HSE 0x0 Timer 8 high step enable
0 High Step register disabled
1 High Step register enabled
D15 R/W T7RSE 0x0 Timer 7 reload step enable
0 Reload Step register disabled
1 Reload Step register enabled
D14 R/W T7LSE 0x0 Timer 7 low step enable
0 Low Step register disabled
1 Low Step register enabled
D13 R/W T7HSE 0x0 Timer 7 high step enable
0 High Step register disabled
1 High Step register enabled
D12 R/W T6RSE 0x0 Timer 6 reload step enable
0 Reload Step register disabled
1 Reload Step register enabled
D11 R/W T6LSE 0x0 Timer 6 low step enable
0 Low Step register disabled
1 Low Step register enabled
D10 R/W T6HSE 0x0 Timer 6 high step enable
0 High Step register disabled
1 High Step register enabled