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I/O HUB MODULE
[Module] DMA TX Buffer Descriptor Pointer
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[ Module] DMA TX Buffer Descriptor Pointer
Addresses: 9000_001C / 9000_801C / 9001_001C / 9001_801C / 9002_001C /
9002_801C / 9003_001C
The DMA TX Buffer Descriptor Pointer is the address of the first buffer descriptor for
each DMA channel.
Register
Register bit
assignment
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[ Module] TX Interrupt Configuration register
Addresses: 9000_0020 / 9000_8020 / 9001_0020 / 9001_8020 / 9002_0020 /
9002_8020 / 9003_0020
The TX Interrupt Configuration register allows system software to configure the
interrupt from the I/O hub module transmit channel.
Register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
TXBDP
TXBDP
Bit(s) Access Mnemonic Reset Description
D31:00 R/W TXBDP 0x0 The first buffer descriptor in the ring. Used when
the W bit is found, which indicates the last buffer
descriptor in the list.
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reser
ved
BLENSTAT
TXTHRS
TXFUFI E TXFURIE TXNCI E TXECI E TXNRI E TXCAIE Reser ved WSTAT I STAT LSTA FSTAT