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SERIAL CONTROL MODULE: HDLC
Interrupt Enable register
424 Hardware Reference NS9215
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Interrupt Enable register
Address: 9002_9004
Use the Interrupt Enable register to enable interrupt generation on specific events.
Enable the interrupt by writing a 1 to the appropriate bit field(s).
Register
Register bit
assignment
D04 R/W LL 0 Local loopback
Provides an internal local loopback feature. When the LL
field is set to 1, the transmit HDLC data signal is
connected to the receive HDLC data signal.
D03:00 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved TBC
Reserv
ed
Not used VCRC RABORT
HINT
Reserv
ed
OFLOW ICRC
RXCLS RBC TX_IDLE RX_IDLE
Bits Access Mnemonic Reset Description
D31:22 R/W Not used 0 Write this field to 0.
D21 R/W HINT 0 Enable HDLC interrupt
Enables interrupt generation directly from the HDLC
module. This is normally handled by hardware.
D20 N/A Reserved N/A N/A
D19 R/W OFLOW 0 Enable overflow error
Enables interrupt generation if the 4-character FIFO in the
HDLC overflows.
Note: This should not happen in a properly configured
system.
D18 R/W ICRC 0 Enable invalid CRC
Enables interrupt generation when a frame is received with
an invalid CRC.
D17 R/W VCRC 0 Enable valid CRC
Enables interrupt generation when a frame is received with
a valid CRC.