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SYSTEM CONTROL MODULE
Timer 5 Control register
www.digiembedded.com 167
Register bit
assignment
Bits Access Mnemonic Reset Description
D31:19 N/A Reserved N/A N/A
D18 R/W Rel mode 0x0 Reload mode
Initializes the timer and the reload value at terminal
count. Reload mode is useful in quadrature decoder
applications, as it allows the reload value to be half
of he terminal count.
0 Use the value in the Reload register
1 Use half the value in the Reload register
D17:16 R/W TM2 0x0 Timer mode 2
00 Mode as set by timer mode 1
01 Reserved
10 Reserved
11 Quadrature decoder/counter mode
D15 R/W TE 0x0 Timer enable
0 Timer disabled
1 Timer enabled
D14:12 R/W Cap Comp 0x0 Capture and compare mode functions
Applicable only when in 16-bit timer mode.
000 Normal operation
001 Compare mode, toggle output on match
010 Compare mode, pulse output on match
011 Capture mode, on input falling edge
100 Capture mode, on input rising edge
101 Capture mode, on every 2
nd
rising edge
110 Capture mode, on every 4
th
rising edge
111 Capture mode, on every 8
th
rising edge
D11 R/W Debug 0x0 Debug mode
0 Timer enabled in CPU debug mode
1 Timer disabled in CPU debug mode
D10 R/W Int Clr 0x0 Interrupt clear
Clears the timer interrupt. Software must write a 1,
then a 0 to this location to clear the interrupt.