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MEMORY CONTROLLER
SDRAM address and data bus interconnect
www.digiembedded.com 229
32-bit wide
configuration
addr[14] A12* A12 A12
addr[15]
addr[16]
addr[17]
addr[18]
addr[19]
addr[20]
addr[21] BA
addr[22] BA0 BA0 BA0 BA0
addr[23] BA1 BA1 BA1 BA1
ap10 A10/AP A10/AP A10/AP A10/AP
data[31:0] D[31:0] D[31:0] D[31:0] D[31:0]
* A12 used only in 4 x 16M x 8 configurations
Signal 16M device
SDRAM
signal
64M device
SDRAM
signal
128M
device
SDRAM
signal
256M
device
SDRAM
signal
512M
device
SDRAM
signal
Signal 16M device
SDRAM
signal
64M device
SDRAM
signal
128M
device
SDRAM
signal
256M
device
SDRAM
signal
512M
device
SDRAM
signal
addr[1]A0A0A0A0A0
addr[2]A1A1A1A1A1
addr[3]A2A2A2A2A2
addr[4]A3A3A3A3A3
addr[5]A4A4A4A4A4
addr[6]A5A5A5A5A5
addr[7]A6A6A6A6A6
addr[8]A7A7A7A7A7
addr[9]A8A8A8A8A8
addr[10] A9 A9 A9 A9 A9
addr[11]
addr[12] A11 A11 A11 A11
addr[13] A12* A12 A12
addr[14]