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System Control Module
CHAPTER 4
The System Control Module configures and oversees system operations for the
processor, and defines both the AMBA High-speed Bus (AHB) arbiter system and
system memory address space.
Features The System Control Module uses the following to configure and maintain system
operations:
AHB arbiter system
System-level address decoding
11 programmable timers
– Watchdog timer
– 10 general purpose timers/counters
Interrupt controller
Multiple configuration and status registers
System Sleep/Wake-up processor
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Bus interconnection
The AMBA AHB bus protocol uses a central multiplexor interconnection scheme. All
bus masters generate the address and control signals that indicate the transfer that
the bus masters want to perform. The arbiter determines which master has its
address and control signals routed to all slaves. A central decoder is required to
control the read data and response multiplexor, which selects the appropriate
signals from the slave that is involved in the transfer.