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ETHERNET COMMUNICATION MODULE
Multicast Address Filter registers
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Multicast Address Filter registers
Each of the eight entries in the multicast address filter logic has individual registers
to hold its 48-bit multicast address. The multicast address for each entry is split
between two registers. Each entry has a register that contains the lower 32 bits of
the multicast address and a separate register that contains the upper 16 bits of the
address. For an explanation of the synchronization scheme used for these registers,
see “Clock synchronization” on page 276.
Multicast Low
Address Filter
Register #0
Address: A060 0A40
Multicast Low
Address Filter
Register #1
Address: A060 0A44
Multicast Low
Address Filter
Register #2
Address: A060 0A48
Multicast Low
Address Filter
Register #3
Address: A060 0A4C
Multicast Low
Address Filter
Register #4
Address: A060 0A50
Multicast Low
Address Filter
Register #5
Address: A060 0A54
D01 W RXFREEB 0 Pool B free bit
D00 W RXFREEA 0 Pool A free bit
Bits Access Mnemonic Reset Description
D31:00 R/W Default = 0x0000 0000 MFILTL0
D31:00 R/W Default = 0x0000 0000 MFILTL1
D31:00 R/W Default = 0x0000 0000 MFILTL2
D31:00 R/W Default = 0x0000 0000 MFILTL4
D31:00 R/W Default = 0x0000 0000 MFILTL4
D31:0 R/W Default = 0x0000 0000 MFILTL5