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WORKING WITH THE CPU
Cache MVA and Set/Way formats
132 Hardware Reference NS9215
ARM926EJ-S
cache format
ARM926EJ-S
cache
associativity
The following points apply to the ARM926EJ-S cache associativity:
The group of tags of the same index defines a set.
The number of tags in a set is the associativity.
The ARM926EJ-S caches are 4-way associative.
The range of tags addressed by the index defines a way.
The number of tags is a way is the number of sets, NSETS.
This table shows values of S and NSETS for an ARM926EJ-S cache.
Set/way/word
format for
ARM926EJ-S
caches
0
1
2
3
4
5
6
7
n
TAG
1
2
31 0
Tag
Index Word Byte
S+5 1S+4 245
0
3
ARM926EJ-S S NSETS
4 KB 5 32
8 KB 6 64
16 KB 7 128
32 KB 8 256
64 KB 9 512
128 KB 10 1024
31 0
Way
31-A
32-A
S+5 S+4 5 4 2 1
SBZ SBZWord
Set select
(= Index)