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WORKING WITH THE CPU
Cache MVA and Set/Way formats
130 Hardware Reference NS9215
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Cache MVA and Set/Way formats
This section shows how the MVA and set/way formats of ARM926EJ-S caches map to
a generic virtually indexed, virtually addressed cache, shown next. The next figure
shows a generic, virtually indexed, virtually addressed cache.
Page
table C
bit
Page
table B
bit
Description ARM926EJ-S behavior
0 0 Noncachable,
nonbufferable
DCache disabled. Read from external memory. Write as a
nonbuffered store(s) to external memory. DCache is not
updated.
0 1 Noncachable,
bufferable
DCache disabled. Read from external memory. Write as a
buffered store(s) to external memory. DCache is not updated.
1 0 Write-through DCache enabled:
Read hit Read from DCache.
Read miss Linefill.
Write hit Write to the DCache, and buffered store to
external memory.
Write miss Buffered store to external memory.
1 1 Write-back DCache enabled:
Read hit Read from DCache.
Read miss Linefill.
Write hit Write to the DCache only.
Write miss Buffered store to external memory.