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12 Hardware Reference NS9215
Low-power SDRAM partial array refresh ...........................................204
Memory map...................................................................................205
Power-on reset memory map ........................................................205
Chip select 1 memory configuration................................................205
Example: Boot from flash, SRAM mapped after boot ............................205
Example: Boot from flash, SDRAM remapped after boot ........................206
Static memory controller....................................................................207
Write protection .......................................................................208
Extended wait transfers ..............................................................208
Memory mapped peripherals.........................................................209
Static memory initialization ................................................................209
Access sequencing and memory width .............................................209
Wait state generation.................................................................209
Programmable enable.................................................................210
Static memory read control.................................................................210
Output enable programmable delay ................................................210
ROM, SRAM, and Flash ................................................................210
Static memory read: Timing and parameters ............................................211
External memory read transfer with zero wait states ...........................211
External memory read transfer with two wait states............................211
External memory read transfer with two output enable delay states.........212
External memory read transfers with zero wait states ..........................212
Burst of zero wait states with fixed length........................................213
Burst of two wait states with fixed length ........................................213
Asynchronous page mode read .............................................................214
Asynchronous page mode read: Timing and parameters ...............................214
External memory page mode read transfer .......................................214
External memory 32-bit burst read from 8-bit memory .........................215
Static memory write control................................................................216
Write enable programming delay ...................................................216
SRAM .....................................................................................216
Static memory Write: Timing and parameters ...........................................216
External memory write transfer with zero wait states ..........................216
External memory write transfer with two wait states...........................217
External memory write transfer with two write enable delay states .........217
Two external memory write transfers with zero wait states ...................218
Flash memory ..........................................................................218
Bus turnaround................................................................................219
Bus turnaround: Timing and parameters..................................................219
Read followed by write with no turnaround.......................................219
Write followed by a read with no turnaround.....................................220
Read followed by a write with two turnaround cycles...........................220
Byte lane control .............................................................................221
Address connectivity .........................................................................222
Memory banks constructed from 8-bit or non-byte-partitioned memory devices