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WORKING WITH THE CPU
Noncachable instruction fetches
134 Hardware Reference NS9215
AHB behavior If instruction prefetching is disabled, all instruction fetches appear on the AHB
interface as single, nonsequential fetches.
If prefetching is enabled, instruction fetches appear either as bursts of four
instructions or as single, nonsequential fetches. No speculative instruction fetching
is done across a 1 KB boundary.
All instruction fetches, including those made in Thumb state, are word transfers (32
bits). In Thumb state, a single-word instruction fetch reads two Thumb instructions
and a four-word burst reads eight instructions.
Instruction
Memory Barrier
Whenever code is treated as data — for example, self-modifying code or loading
code into memory — a sequence of instructions called an instruction memory
barrier (IMB) operation must be used to ensure consistency between the data and
instruction streams processed by the ARM926EJ-S processor.
Usually the instruction and data streams are considered to be completely
independent by the ARM926EJ-S processor memory system, and any changes in the
data side are not automatically reflected in the instruction side. For example, if
code is modified in main memory, ICache may contain stale entries. To remove
these stale entries, part of all of the ICache must be invalidated.
IMB operation Use this procedure to ensure consistency between data and instruction sides:
1 Clean the DCache. If the cache contains cache lines corresponding to write-back
regions of memory, it might contain dirty entries. These entries must be cleaned
to make external memory consistent with the DCache. If only a small part of the
cache has to be cleaned, it can be done by using a sequence of clean DCache
single entry instructions. If the entire cache has to be cleaned, you can use the
test and clean operation (see "R7:Cache Operations register," beginning on page
94).
2 Drain the write buffer. Executing a drain write buffer causes the ARM926EJ-S
core to wait until outstanding buffered writes have completed on the AHB
interface. This includes writes that occur as a result of data being written back
to main memory because of clean operations, and data for store instructions.
3 Synchronize data and instruction streams in level two AHB systems. The
level two AHB subsystem might require synchronization between data and
instruction sides. It is possible for the data and instruction AHB masters to be
attached to different AHB subsystems. Even if both masters are present on the
same bus, some form of separate ICache might exist for performance reasons;
this must be invalidated to ensure consistency.
The process of synchronizing instructions and data in level two memory
must be invoked using some form of fully blocking operation, to ensure that
the end of the operation can be determined using software. It is