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TIMING
Reset and hardware strapping timing
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Reset and hardware strapping timing
All AC characteristics are measured with 10pF, unless otherwise noted.
The next table describes the values shown in the IEEE 1284 timing diagram.
Note: The hardware strapping pins are latched 5 clock cycles after reset_n is deasserted (goes high).
Parm Description Min Typ Unit Notes
R1 reset_n minimum time 10 x1_sys_osc
clock cycles
1
R2 reset_n to reset_done NOR flash: 4.5
SPI flash: 15
ms
R1
R2
x1_sys_osc
reset_n
reset_done