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ETHERNET COMMUNICATION MODULE
RX_A Buffer Descriptor Pointer Offset register
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Register bit
assignment
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RX_A Buffer Descriptor Pointer Offset register
Address: A060 0A28
Register
Register bit
assignment
Bits Access Mnemonic Reset Description
D31:08 N/A Reserved N/A N/A
D07:00 R TXSPTR 0x00 If the TX runs out of frames to send, it sets TXIDLE in the
Ethernet Interrupt Status register and stores the pointer (in
the TX buffer descriptor RAM) to the buffer descriptor
that did not have its F bit set in the TX Stall Buffer
Descriptor Pointer register.
Note: This pointer is the 8-bit physical address of the
TX buffer descriptor RAM, and points to the
first location of the four-location buffer
descriptor. The byte offset of this buffer
descriptor can be calculated by multiplying this
value by 4.
Note: Software uses TXSPTR to identify the entry in
the TX buffer descriptor RAM at which the TX
stalled.
Reserved
RXAOFF
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Bits Access Mnemonic Reset Description
D31:11 N/A Reserved N/A N/A
D10:00 R RXAOFF 0x000 Contains an 11-bit byte offset from the start of the pool A
ring. The offset is updated at the end of the RX packet,
and will have the offset to the next buffer descriptor that
will be used. RXAOFF can be used to determine where
the
RX_RD logic will put the next packet.