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10 Hardware Reference Manual
Contents
8.2.5 Rx_Thread_Freelist_Timeout_# .......................................................................... 256
8.2.6 Receive Operation Summary............................................................................... 256
8.2.7 Receive Flow Control Status ............................................................................... 258
8.2.7.1 SPI-4.................................................................................................... 258
8.2.7.2 CSIX..................................................................................................... 259
8.2.7.2.1 Link-Level............................................................................. 259
8.2.7.2.2 Virtual Output Queue ........................................................... 260
8.2.8 Parity.................................................................................................................... 260
8.2.8.1 SPI-4.................................................................................................... 260
8.2.8.2 CSIX..................................................................................................... 261
8.2.8.2.1 Horizontal Parity................................................................... 261
8.2.8.2.2 Vertical Parity....................................................................... 261
8.2.9 Error Cases.......................................................................................................... 261
8.3 Transmit............................................................................................................................ 262
8.3.1 Transmit Pins....................................................................................................... 262
8.3.2 TBUF ................................................................................................................... 263
8.3.2.1 SPI-4.................................................................................................... 266
8.3.2.2 CSIX..................................................................................................... 267
8.3.3 Transmit Operation Summary.............................................................................. 268
8.3.3.1 SPI-4.................................................................................................... 268
8.3.3.2 CSIX..................................................................................................... 269
8.3.3.3 Transmit Summary............................................................................... 270
8.3.4 Transmit Flow Control Status .............................................................................. 270
8.3.4.1 SPI-4.................................................................................................... 271
8.3.4.2 CSIX..................................................................................................... 273
8.3.4.2.1 Link-Level............................................................................. 273
8.3.4.2.2 Virtual Output Queue ........................................................... 273
8.3.5 Parity.................................................................................................................... 273
8.3.5.1 SPI-4.................................................................................................... 273
8.3.5.2 CSIX..................................................................................................... 274
8.3.5.2.1 Horizontal Parity................................................................... 274
8.3.5.2.2 Vertical Parity....................................................................... 274
8.4 RBUF and TBUF Summary .............................................................................................. 274
8.5 CSIX Flow Control Interface ............................................................................................. 275
8.5.1 TXCSRB and RXCSRB Signals .......................................................................... 275
8.5.2 FCIFIFO and FCEFIFO Buffers ........................................................................... 276
8.5.2.1 Full Duplex CSIX.................................................................................. 277
8.5.2.2 Simplex CSIX....................................................................................... 278
8.5.3 TXCDAT/RXCDAT, TXCSOF/RXCSOF, TXCPAR/RXCPAR,
and TXCFC/RXCFC Signals................................................................................ 280
8.6 Deskew and Training........................................................................................................ 280
8.6.1 Data Training Pattern........................................................................................... 282
8.6.2 Flow Control Training Pattern .............................................................................. 282
8.6.3 Use of Dynamic Training ..................................................................................... 283
8.7 CSIX Startup Sequence.................................................................................................... 287
8.7.1 CSIX Full Duplex ................................................................................................. 287
8.7.1.1 Ingress IXP2800 Network Processor ................................................... 287
8.7.1.2 Egress IXP2800 Network Processor.................................................... 287
8.7.1.3 Single IXP2800 Network Processor..................................................... 288
8.7.2 CSIX Simplex....................................................................................................... 288
8.7.2.1 Ingress IXP2800 Network Processor ................................................... 288
8.7.2.2 Egress IXP2800 Network Processor.................................................... 289