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72 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
For PCI to DRAM transfers, the PCI command is Memory Read, Memory Read line, or Memory
Read Multiple. For DRAM to PCI transfers, the PCI command is Memory Write. Memory Write
Invalidate is not supported.
Up to two DMA channels are running at a time with three descriptors outstanding. Effectively, the
active channels interleave bursts to or from the PCI Bus.
Interrupts are generated at the end of DMA operation for the Intel XScale
®
core. However,
Microengines do not provide an interrupt mechanism. The DMA Channel will instead use an Event
Signal to notify the particular Microengine on completion of DMA.
2.9.3.1 DMA Descriptor
Each descriptor uses four 32-bit words in SRAM, aligned on a 16-byte boundary. The DMA
channels read the descriptors from SRAM into working registers once the control register has been
set to initiate the transaction. This control must be set explicitly; this starts the DMA transfer.
Register names for DMA channels are listed in Figure 15 and Table 17 lists the descriptor contents.
After a descriptor is processed, the next descriptor is loaded in the working registers. This process
repeats until the chain of descriptors is terminated (i.e., the End of Chain bit is set).
Figure 15. DMA Descriptor Reads
A9368-01
DMA Channel Register
Working Register
Byte Count Register
PCI Address Register
DRAM Address REgister
Descriptor Pointer Register
CHAN_X_BYTE_COUNT
CHAN_X_PCI_ADDR
CHAN_X_DRAM_ADDR
CHAN_X_DESC_PTR
Channel Register Name
(X can be 1, 2, or 3)
DMA Channel Register
Control Register
Control Register CHAN_X_CONTROL
Channel Register Name
(X can be 1, 2, or 3)
4
1
2
3
Current Descriptor
Prior Descriptor
Last Descriptor
Next Descriptor
Local SRAM
Table 17. DMA Descriptor Format
Offset from Descriptor Pointer Description
0x0 Byte Count
0x4 PCI Address
0x8 DRAM Address
0xC Next Descriptor Address