Filter
Top Products
366 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Clocks and Reset
10.3.2 PCI-Initiated Reset
CFG_RST_DIR is not asserted and PCI_RST_L is asserted.
When the CFG_RST_DIR strap pin is not asserted (sampled 0), PCI_RST_L is input to the
IXP2800 Network Processor and is used to reset all the internal functions. Its behavior is the same
as a hardware reset using nRESET pin.
10.3.3 Watchdog Timer-Initiated Reset
The IXP2800 Network Processor provides a watchdog timer that can cause a reset if the Watchdog
timer expires and the Watchdog enable bit WDE in the Timer Watchdog Enable register is also set.
The Intel XScale
®
core should be programmed to reset the watch dog timer periodically to ensure
that it does not expire. If a watchdog timer expires, it is assumed that the Intel XScale
®
core has
ceased executing instructions properly. When the timer expires, the Watchdog History
register bit[0] is set which can be read by the software later on.
The following sections define IXP2800 Network Processor behavior for the watchdog event.
Figure 134. Reset Generation
A9781-01
Reset
PLL_RST
CORE_RST
PLL
Logic
D
PCI_RST#
WATCHDOG_RESET
nRESET#
SOFTWARE RESET
Watchdog History
Register (WHR)
Watchdog Event
CFG_PCI_RST_DIR
(1: Output, 0:Input)
Counter to
guarantee
minimum
assertion
time
Notes:
When Watchdog event happens the register gets set.
This register gets reset when WHR_Reset gets asserted or software reads it.