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400 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
97 Rx null autopush P_CLK pulse separate
98 Tx skip P_CLK pulse separate
An mpacket was dropped due to the
Tx_Skip bit being set in the Transmit Control
Word.
99 SF_CRDY P_CLK level separate
Only valid in CSIX receive mode and
indicates how much of the time the switch
fabric is able to receive control CFrames.
100 SF_DRDY P_CLK level separate
Only valid in CSIX receive mode and
indicates how much of the time the switch
fabric is able to receive data CFrames.
101 TM_CRDY P_CLK level separate
Only valid in CSIX receive mode; indicates
how much of the time the egress processor
is able to receive control CFrames.
102 TM_DRDY P_CLK level separate
Only valid in CSIX receive mode; indicates
how much of the time the egress processor
is able to receive data CFrames.
103 FCIFIFO enqueue P_CLK pulse separate
104 FCIFIFO dequeue P_CLK pulse separate
105 FCIFIFO error P_CLK pulse separate
Indicates that a bad CFrame was received
on the CBus (horizontal or vertical parity
error, premature RxSOF); only valid in CSIX
transmit mode.
106
FCIFIFO synchronizing
FIFO error
P_CLK pulse separate
Indicates that the CBus ingress logic
encountered a FCIFIFO full condition while
enqueueing a CFrame into FCIFIFO.
107 Vertical parity error P_CLK pulse separate Only valid in CSIX receive mode.
108 Horizontal parity P_CLK pulse separate Only valid in CSIX receive mode.
109 Dip 4 Parity Error P_CLK pulse separate Only valid in SPI-4 receive mode.
110 Dip 2 Parity Error P_CLK pulse separate Only valid in SPI-4 receive mode.
111 reserved
112 CSIX DATA receive active MR_CLK level separate
Indicates a valid CSIX DATA CFRAME
received on the RX_DATA bus and may be
used to measure bus utilization; the active
signal from the MR_CLK domain is
synchronized; as such, it yields an
approximate value.
113
CSIX CONTROL
receive active
MR_CLK level separate
Indicates a valid CSIX CONTROL CFRAME
received on the RX_DATA bus and may be
used to measure bus utilization; the active
signal from the MR_CLK domain is
synchronized; as such, it yields an
approximate value.
114 SPI-4 receive active MR_CLK level separate
Indicates a valid SPI-4 Packet received on
the RX_DATA bus and may be used to
measure bus utilization; the active signal
from the MR_CLK domain is synchronized;
as such, it yields an approximate value.
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 5 of 6)