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302 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
As threads complete processing of the data in a buffer, the buffer is returned to a free list.
Subsequently, the thread also returns to a separate free list. The return of buffers and threads to the
free lists may occur in a different order than the order of their removal.
All SPI-4.2 ports sharing the interface have equal access to the buffering resources. Flow control
can transition to a non-starving state when 25%, 50%, 75%, or 87.5% of the buffers are consumed,
as configured by HWM_Control[RBUF_S_HWM]. At this point, the remaining buffers are
available and, additionally, 2K bytes of packed FIFO (corresponding to 128 SPI-4.2 credits) are
available for incoming data storage. If receiver flow control is expected to be asserted and for a
sufficiently large number of ports and values of MaxBurst1 or MaxBurst2, it may be necessary for
the PHY device to discard credits already granted if a state of Satisfied is reported by the network
processor to the device, treating the Satisfied state more as an XOFF state. Otherwise, excessive
credits may be outstanding for the storage available and receiver overruns may occur.
For more information about the SPI-4.2 receiver, see Section 8.2.7.
8.9.3.2 SPI-4.2 Transmitter
The network processor transmitter transfers SPI-4.2 bursts from transmitter buffers. The buffers
may be configured as 128 buffers of 64 bytes, 64 buffers of 128 bytes, or 32 buffers of 256 bytes.
The control word information and other control information for the burst are stored in additional
control storage. The buffers are always transmitted in a fixed order. Software can determine the
index of the last buffer transmitted, and keep track of the last buffer committed to the transmitter.
The transmitter buffers are used as a ring, with the “get index” updated by the transmitter and the
“put index” updated due to committing a buffer element to transmission.
Each transmit buffer supports a limited gather capability to stitch together a protocol header and a
payload. The buffer supports independent prefix (or prepended) data and payload data. The prefix
data can begin at any offset from 0 to 7 and have a length of from 0 to 31 bytes. The payload begins
at an offset of 0 to 7 bytes from the next octal-byte boundary following the prefix and can fill out
the remainder of the buffer. For more complicated merging or shifting of data within a burst, the
data should be passed through a Microengine to perform any arbitrary merging and/or shifting.
Buffers may be statically allocated to different ports in an inter-leaved fashion so that bandwidth
availability is balanced for each of the ports. Transmit buffers may be flagged to be skipped if no
data is available for a particular port.
The transmitter scheduler, implemented on a Microengine, is responsible for reacting to the status
information provided by the PHY device. The status information can be read via registers. The
status information is available in two formats: a single status per register and status for 16 ports in
a single register. For more information, see Section 8.3.4, “Transmit Flow Control Status” on
page 270.