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Hardware Reference Manual 329
Intel
®
IXP2800 Network Processor
PCI Unit
9.2.6.6 Special Cycle
As an initiator, special cycles are broadcast to all PCI agents, so DEVSEL_L is not asserted and no
error can be received.
9.2.7 PCI Fast Back-to-Back Cycles
The core supports fast back-to-back target cycles on the PCI Bus. The core does not generate
initiator fast back-to-back cycles on the PCI Bus regardless of the value in the fast back-to-back
enable bit of the Status and Command register in the PCI configuration space.
9.2.8 PCI Retry
As a slave, the PCI Unit generates retry on:
• A slave write when the Data write FIFO is full.
• When address FIFO is full
• Data read is handled as delay transactions. If the HOG_MODE bit is set in the
PCI_CONTROL register, the bus will be held for 16 PCI clocks before asserting retry.
As an initiator, the core supports retry by maintaining an internal counter of the current address. On
receiving a retry, the core de-asserts PciFrameN and then re-assert PciFrameN with the current
address from the counter.
9.2.9 PCI Disconnect
As a slave, it disconnects for the following conditions:
• Bursted PCI configuration cycle.
• Bursted access to PCI_CSR_BAR.
• PCI reads past the amount of data in the read FIFO.
• PCI burst cycles that cross 1K PCI address boundary which includes PCI burst cycles that
cross memory decodes from the core as a target to decodes that are outside the core (e.g.,
started inside a BAR and ends outside of that BAR).
As an initiator, the core supports retry and disconnect by maintaining an internal counter of the
current address. On receiving a retry or disconnect, the core de-asserts PciFrameN and then re-
assert PciFrameN with the current address + “current transfer byte size” from the counter.
9.2.10 PCI Built-In System Test
The IXP2800 Network Processor supports BIST when there is an external PCI host. The PCI host
will set the STRT bit in the PCI_CACHE_LAT_HDR_BIST configuration register. An interrupt is
generated to the Intel XScale
®
core if it is enabled by the Intel XScale
®
core Interrupt Enable
register. The Intel XScale
®
core software can respond to the interrupt by running an application-
specific test. Upon successful completion of the test, the Intel XScale
®
core will reset the STRT bit.
If this bit is not reset two seconds after the PCI host sets the STRT bit, the host will indicate that the
Network Processor failed the test.