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Hardware Reference Manual 71
Intel
®
IXP2800 Network Processor
Technical Description
2.9 PCI Controller
The PCI Controller provides a 64-bit, 66 MHz capable PCI Local Bus Revision 2.2 interface, and is
compatible to 32-bit or 33 MHz PCI devices. The PCI controller provides the following functions:
• Target Access (external Bus Master access to SRAM, DRAM, and CSRs)
• Master Access (the Intel XScale
®
core access to PCI Target devices)
• Two DMA Channels
• Mailbox and Doorbell registers for the Intel XScale
®
core to Host communication
• PCI arbiter
The IXP2800 Network Processor can be configured to act as PCI central function (for use in a
stand-alone system), where it provides the PCI reset signal, or as an add-in device, where it uses the
PCI reset signal as the chip reset input. The choice is made by connecting the cfg_rst_dir input pin
low or high.
2.9.1 Target Access
There are three Base Address Registers (BARs) to allow PCI Bus Masters to access SRAM,
DRAM, and CSRs, respectively. Examples of PCI Bus Masters include a Host Processor (for
example a Pentium
®
processor), or an I/O device such as an Ethernet controller, SCSI controller, or
encryption coprocessor.
The SRAM BAR can be programmed to sizes of 16, 32, 64, 128, or 256 Mbytes, or no access.
The DRAM BAR can be programmed to sizes of 128, 256, or 512 Mbytes or 1 Gbyte, or no access.
The CSR BAR is 8 KB.
PCI Boot Mode is supported, in which the Host downloads the Intel XScale
®
core boot image into
DRAM, while holding the Intel XScale
®
core in reset. Once the boot image has been loaded, the
Intel XScale
®
core reset is deasserted. The alternative is to provide the boot image in a Flash ROM
attached to the Slowport.
2.9.2 Master Access
The Intel XScale
®
core and Microengines can directly access the PCI bus. The Intel XScale
®
core
can do loads and stores to specific address regions to generate all PCI command types.
Microengines use PCI instruction, and also use address regions to generate different PCI
commands.
2.9.3 DMA Channels
There are two DMA Channels, each of which can move blocks of data from DRAM to the PCI or
from the PCI to DRAM. The DMA channels read parameters from a list of descriptors in SRAM,
perform the data movement to or from DRAM, and stop when the list is exhausted. The descriptors
are loaded from predefined SRAM entries or may be set directly by CSR writes to DMA Channel
registers. There is no restriction on byte alignment of the source address or the destination address.