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350 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
9.5.2.2 DMA Read from SRAM (Descriptor Read) Gets a Memory Error
1. Set PCI_CONTROL[DMA_SRAM_ERR] which will interrupt the Intel XScale
®
core if
enabled.
2. Master Interface clears the Channel Enable bit in CHAN_X_CONTROL.
3. Master Interface sets DMA channel error bit in CHAN_X_CONTROL.
4. Master Interface does not reset the DMA CSRs; This leaves the descriptor pointer pointing to
the DMA descriptor of the failed transfer.
5. Master Interface resets the state machines and DMA buffers.
9.5.2.3 DMA from DRAM Transfer (Write to PCI) Receives PCI_PERR_L on
PCI Bus
1. If PCI_CMD_STAT[PERR_RESP] is not set, PCI Unit will ignore the parity error.
2. If PCI_CMD_STAT[PERR_RESP] is set:
a. Master Interface sets PCI_CONTROL[DPE] which will interrupt the Intel XScale
®
core
if enabled.
b. Master Interface clears the Channel Enable bit in CHAN_X_CONTROL.
c. Master Interface sets DMA channel error bit in CHAN_X_CONTROL.
d. Master Interface does not reset the DMA CSRs; This leaves the descriptor pointer
pointing to the DMA descriptor of the failed transfer.
e. Master Interface resets the state machines and DMA buffers.
f. Core sets PCI_CMD_STAT[PERR] if properly enabled.
9.5.2.4 DMA To DRAM (Read from PCI) Has Bad Data Parity
1. If PCI_CMD_STAT[PERR_RESP] is not set, PCI Unit will ignore the parity error.
2. If PCI_CMD_STAT[PERR_RESP] is set:
a. Core asserts PCI_PERR_L on PCI if PCI_CMD_STAT[PERR_RESP] is set.
b. Master Interface sets PCI_CONTROL[DPED] which can interrupt the Intel XScale
®
core
if enabled.
c. Master Interface clears the Channel Enable bit in CHAN_X_CONTROL.
d. Master Interface sets DMA channel error bit in CHAN_X_CONTROL.
e. Master Interface does not reset the DMA CSRs; This leaves the descriptor pointer
pointing to the DMA descriptor of the failed transfer.
f. Master Interface resets the state machines and DMA buffers.