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418 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
11.4.6.22 SRAM DP1 Events Target ID(001001) / Design Block #(0010)
11.4.6.23 SRAM DP0 Events Target ID(001010) / Design Block #(0010)
Table 176. SRAM DP1 PMU Event List
Event
Number
Event Name
Clock
Domain
Pulse/
Level
Burst Description
Note:
1. SRAM DP1/DP0 push/pull arbiter has same event lists.
2. S_CLK = SRAM clock domain
3. P_CLK = PP clock domain
signals that begin with sps_ correspond to S_Push Arb
signals that begin with spl_ correspond to S_Pull Arb
signals that contain _pc_ (after the unit designation) correspond to the PCI target interface
signals that contain _m_ (after the unit designation) correspond to the MSF target interface
signals that contain _sh_ (after the unit designation) correspond to the SHaC target interface
signals that contain _s0_ (after the unit designation) correspond to the SRAM0 target interface
signals that contain _s1_ (after the unit designation) correspond to the SRAM1 target interface
signals that contain _s2_ (after the unit designation) correspond to the SRAM2 target interface
signals that contain _s3_ (after the unit designation) correspond to the SRAM3 target interface
Table 177. SRAM DP0 PMU Event List (Sheet 1 of 3)
Event
Number
Event Name
Clock
Domain
Single
pulse/
Long
pulse
Burst Description
0 sps_pc_cmd_valid_rph P_CLK Long separate PCI Push Command Queue FIFO Valid
1 sps_pc_enq_wph P_CLK single separate PCI Push Command Queue FIFO Enqueue
2 sps_pc_deq_wph P_CLK single separate PCI Push Command Queue FIFO Dequeue
3 sps_pc_push_q_full_wph P_CLK Long separate PCI Push Command Queue FIFO Full
4 sps_m_cmd_valid_rph P_CLK Long separate MSF Push Command Queue FIFO Valid
5 sps_m_enq_wph P_CLK single separate MSF Push Command Queue FIFO Enqueue
6 sps_m_deq_wph P_CLK single separate MSF Push Command Queue FIFO Dequeue
7 sps_m_push_q_full_wph P_CLK Long separate MSF Push Command Queue FIFO Full
8 sps_sh_cmd_valid_rph P_CLK Long separate SHaC Push Command Queue FIFO Valid
9 sps_sh_enq_wph P_CLK single separate SHaC Push Command Queue FIFO Enqueue
10 sps_sh_deq_wph P_CLK single separate
SHaC Push Command Queue FIFO
Dequeue
11 sps_sh_push_q_full_wph P_CLK Long separate SHaC Push Command Queue FIFO Full
12 sps_s0_cmd_valid_rph P_CLK Long separate SRAM0 Push Command Queue FIFO Valid