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Hardware Reference Manual 351
Intel
®
IXP2800 Network Processor
PCI Unit
9.5.2.5 DMA Transfer Experiences a Master Abort (Time-Out) on PCI
Note: That is, nobody asserts DEVSEL during the DEVSEL window.
1. Master Interface sets PCI_CONTROL[RMA] which will interrupt the Intel XScale
®
core if
enabled.
2. Master Interface clears the Channel Enable bit in CHAN_X_CONTROL.
3. Master Interface sets DMA channel error bit in CHAN_X_CONTROL.
4. Master Interface does not reset the DMA CSRs; This leaves the descriptor pointer pointing to
the DMA descriptor of the failed transfer.
5. Master Interface resets the state machines and DMA buffers
9.5.2.6 DMA Transfer Receives a Target Abort Response During a
Data Phase
1. Core terminates the transaction.
2. Master Interface sets PCI_CONTROL[RTA] which can interrupt the Intel XScale
®
core if
enabled.
3. Master Interface clears the Channel Enable bit in CHAN_X_CONTROL.
4. Master Interface sets DMA channel error bit in CHAN_X_CONTROL.
5. Master Interface does not reset the DMA CSRs; This leaves the descriptor pointer pointing to
the DMA descriptor of the failed transfer.
6. Master Interface resets the state machines and DMA buffers.
9.5.2.7 DMA Descriptor Has a 0x0 Word Count (Not an Error)
1. No data is transferred.
2. Descriptor is retired normally.
9.5.3 As a PCI Initiator During a Direct Access from the Intel
XScale
®
Core or Microengine
9.5.3.1 Master Transfer Experiences a Master Abort (Time-Out) on PCI
1. Core aborts the transaction.
2. Master Interface sets PCI_CONTROL[RMA] which will interrupt the Intel XScale
®
core if
enabled.
9.5.3.2 Master Transfer Receives a Target Abort Response During
a Data Phase
1. Core aborts the transaction.
2. Master Interface sets PCI_CONTROL[RTA] which will interrupt the Intel XScale
®
core if
enabled.