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Hardware Reference Manual 291
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN
Register for Instruction:
msf[read, $s_xfer_reg, src_op_1, src_op_2, ref_cnt], optional_token
For transfers to a Microengine, the MSF acts as a target. Commands from Microengines and the
Intel XScale
®
core are received on the command bus. The commands are checked to see if they are
targeted to the MSF. If so, they are enqueued into the Command Inlet FIFO, and then moved to the
Read Cmd FIFO. When the Command Inlet FIFO is nearly full, it asserts a signal to the command
arbiters. The command arbiters prevent further commands to the MSF until after the full signal is
asserted. The RBUF element or CSR specified in the address field of the command is read and the
data is registered in the SPUSH_DATA register. The control logic then arbitrates for
S_PUSH_BUS, and when granted, it drives the data.
8.8.2 Microengine S_TRANSFER_OUT Register to TBUF or
MSF CSR for Instruction:
msf[write, $s_xfer_reg, src_op_1, src_op_2, ref_cnt], optional_token
For transfers from a Microengine, the MSF acts as a target. Commands from Microengines are
received on the two command buses. The commands are checked to see if they are targeted to the
MSF. If so, they are enqueued into the Command Inlet FIFO, and then moved to the Write Cmd
FIFO. When the Command Inlet FIFO is nearly full, it asserts a signal to the command arbiters.
The command arbiters prevent further commands to the MSF until after the full signal is asserted.
The control logic then arbitrates for S_PULL_BUS, and when granted, it receives and registers the
data from the Microengine into the S_PULL_DATA register. It then writes that data into the TBUF
element or CSR specified in the address field of the command.
8.8.3 Microengine to MSF CSR for Instruction:
msf[fast_write, src_op_1, src_op_2]
For fast write transfers from the Microengine, the MSF acts as a target. Commands from
Microengines are received on the two command buses. The commands are checked to see if they
are targeted to the MSF. If so, they are enqueued into the Command Inlet FIFO, and then moved to
the Write Cmd FIFO. When the Command Inlet FIFO is nearly full, it asserts a signal to the
command arbiters. The command arbiters prevent further commands to the MSF until after the full
signal is asserted. The control logic uses the address and data, both found in the address field of the
command. It then writes the data into the CSR specified.
8.8.4 From RBUF to DRAM for Instruction:
dram[rbuf_rd, --, src_op1, src_op2, ref_cnt], indirect_ref
For the transfers to DRAM, the RBUF acts like a slave. The address of the data to be read is given
in D_PULL_ID. The data is read from RBUF and registered in the D_PULL_DATA register. It is
then multiplexed and driven to the DRAM channel on D_PULL_BUS.