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14 Hardware Reference Manual
Contents
10.3.2 PCI-Initiated Reset............................................................................................... 366
10.3.3 Watchdog Timer-Initiated Reset .......................................................................... 366
10.3.3.1 Slave Network Processor (Non-Central Function) ............................... 367
10.3.3.2 Master Network Processor (PCI Host, Central Function) .................... 367
10.3.3.3 Master Network Processor (Central Function)..................................... 367
10.3.4 Software-Initiated Reset ...................................................................................... 367
10.3.5 Reset Removal Operation Based on CFG_PROM_BOOT.................................. 368
10.3.5.1 When CFG_PROM_BOOT is 1 (BOOT_PROM is Present) ................ 368
10.3.5.2 When CFG_PROM_BOOT is 0 (BOOT_PROM is Not Present) ......... 368
10.3.6 Strap Pins ............................................................................................................ 368
10.3.7 Powerup Reset Sequence ................................................................................... 370
10.4 Boot Mode ........................................................................................................................ 370
10.4.1 Flash ROM........................................................................................................... 372
10.4.2 PCI Host Download ............................................................................................. 372
10.5 Initialization ....................................................................................................................... 373
11 Performance Monitor Unit ........................................................................................................ 375
11.1 Introduction ....................................................................................................................... 375
11.1.1 Motivation for Performance Monitors................................................................... 375
11.1.2 Motivation for Choosing CHAP Counters ............................................................ 376
11.1.3 Functional Overview of CHAP Counters.............................................................. 377
11.1.4 Basic Operation of the Performance Monitor Unit ............................................... 378
11.1.5 Definition of CHAP Terminology .......................................................................... 379
11.1.6 Definition of Clock Domains................................................................................. 380
11.2 Interface and CSR Description ......................................................................................... 380
11.2.1 APB Peripheral .................................................................................................... 381
11.2.2 CAP Description .................................................................................................. 381
11.2.2.1 Selecting the Access Mode.................................................................. 381
11.2.2.2 PMU CSR ............................................................................................ 381
11.2.2.3 CAP Writes .......................................................................................... 381
11.2.2.4 CAP Reads .......................................................................................... 381
11.2.3 Configuration Registers ....................................................................................... 382
11.3 Performance Measurements ............................................................................................ 382
11.4 Events Monitored in Hardware ......................................................................................... 385
11.4.1 Queue Statistics Events....................................................................................... 385
11.4.1.1 Queue Latency..................................................................................... 385
11.4.1.2 Queue Utilization.................................................................................. 385
11.4.2 Count Events ....................................................................................................... 385
11.4.2.1 Hardware Block Execution Count ........................................................ 385
11.4.3 Design Block Select Definitions ........................................................................... 386
11.4.4 Null Event ............................................................................................................ 387
11.4.5 Threshold Events................................................................................................. 388
11.4.6 External Input Events........................................................................................... 389
11.4.6.1 XPI Events Target ID(000001) / Design Block #(0100) ....................... 389
11.4.6.2 SHaC Events Target ID(000010) / Design Block #(0101).................... 393
11.4.6.3 IXP2800 Network Processor MSF Events Target ID(000011) /
Design Block #(0110)........................................................................... 396
11.4.6.4 Intel XScale® Core Events Target ID(000100) /
Design Block #(0111)........................................................................... 402
11.4.6.5 PCI Events Target ID(000101) / Design Block #(1000) ....................... 405
11.4.6.6 ME00 Events Target ID(100000) / Design Block #(1001).................... 409