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Hardware Reference Manual 27
Intel
®
IXP2800 Network Processor
Technical Description
Technical Description 2
2.1 Overview
This section provides a brief overview of the IXP2800 Network Processor internal hardware.
This section is intended as an overall hardware introduction to the network processor.
The major blocks are:
• Intel XScale
®
core — General purpose 32-bit RISC processor (ARM* Version 5 Architecture
compliant) used to initialize and manage the network processor, and can be used for higher
layer network processing tasks.
• Intel XScale
®
technology Peripherals (XPI) — Interrupt Controller, Timers, UART, General
Purpose I/O (GPIO) and interface to low-speed off chip peripherals (such as maintenance port
of network devices) and Flash ROM.
• Microengines (MEs) — Sixteen 32-bit programmable engines specialized for Network
Processing. Microengines do the main data plane processing per packet.
• DRAM Controllers — Three independent controllers for Rambus* DRAM. Typically DRAM
is used for data buffer storage.
• SRAM Controllers — Four independent controllers for QDR SRAM. Typically SRAM is used
for control information storage.
• Scratchpad Memory — 16 Kbytes storage for general purpose use.
• Hash Unit — Polynomial hash accelerator. The Intel XScale
®
core and Microengines can use
it to offload hash calculations.
• Control and Status Register Access Proxy (CAP) — These provide special inter-processor
communication features to allow flexible and efficient inter-Microengine and Microengine to
Intel XScale
®
core communication.
• Media and Switch Fabric Interface (MSF) — Interface for network framers and/or Switch
Fabric. Contains receive and transmit buffers.
• PCI Controller — PCI Local Bus Specification, Version 2.2* interface for 64-bit 66-MHz I/O. PCI can
be used to either connect to a Host processor, or to attach PCI-compliant peripheral devices.
• Performance Monitor — Counters that can be programmed to count selected internal chip
hardware events, which can be used to analyze and tune performance.
Figure 1 is a simple block diagram of the network processor showing the major internal hardware
blocks. Figure 2 is a detailed diagram of the network processor units and buses.