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88 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
Figure 17 illustrates locked entries in TLB.
3.4 Instruction Cache
The Intel XScale
®
core instruction cache enhances performance by reducing the number of
instruction fetches from external memory. The cache provides fast execution of cached code. Code
can also be locked down when guaranteed or fast access time is required.
Figure 18 shows the cache organization and how the instruction address is used to access the cache.
The instruction cache is a 32-Kbyte, 32-way set associative cache; this means there are 32 sets with
each set containing 32 ways. Each way of a set contains eight 32-bit words and one valid bit, which
is referred to as a line. The replacement policy is a round-robin algorithm and the cache also
supports the ability to lock code in at a line granularity.
Figure 17. Example of Locked Entries in TLB
A9684-01
Locked
Note: 8 entries locked, 24 entries available for round robin replacement
entry 0
entry 1
entry 7
entry 8
entry 22
entry 23
entry 30
entry 31