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Hardware Reference Manual 325
Intel
®
IXP2800 Network Processor
PCI Unit
9.2.3 PCI Type 0 Configuration Cycles
A PCI access to a configuration register occurs when the following conditions are satisfied:
• PCI_IDSEL is asserted. (PCI_IDSEL only supports PCI_AD[23:16] bits).
• The PCI command is a configuration write or read.
• The PCI_AD [1:0] are 00.
A configuration register is selected by PCI_AD[7:2]. If the PCI master attempts to do a burst
longer than one 32-bit Dword, the PCI unit signals a target disconnect. PCI unit does not issue
PCI_ACK64 for configuration cycle.
9.2.3.1 Configuration Write
A write occurs if the PCI command is a Configuration Write. The PCI byte-enables determine
which bytes are written.If a nonexistent configuration register is selected within the configuration
register address range, the data is discarded and no error action is taken.
9.2.3.2 Configuration Read
A read occurs if the PCI command is a Configuration Read. The data from the configuration
register selected by PCI_AD[7:2] is returned on PCI_AD[31:0]. If a nonexistent configuration
register is selected within the configuration register address range, the data returned are zeros and
no error action is taken.
9.2.4 PCI 64-Bit Bus Extension
The PCI Unit is in 64-bit mode when PCI_REQ64_L is sampled active on the de-assertion edge of
PCI Reset. These are the general rules in assertions of PCI_REQ64_L and PCI_ACK64_L:
As a target:
1. PCI Unit asserts PCI_ACK64_L only in 64-bit mode.
2. PCI Unit asserts PCI_ACK64_L only to target cycles that matches the PCI_SRAM_BAR and
PCI_DRAM_BAR and a 64-bit transaction is negotiated.
3. PCI Unit does not assert PCI_ACK64_L target cycles that matches the PCI_CSR_BAR even a
64-bit transaction is negotiated.
As an initiator:
1. PCI Unit asserts PCI_REQ64_L only in 64-bit mode.
2. PCI Unit asserts PCI_REQ64_L to negotiate a 64-bit transaction only if the address is double
Dword aligned (PCI_AD[2] must be 0 during the address phase).
3. If the target responses to PCI_REQ64_L with PCI_ACK64_L de-asserted, PCI Unit will
complete the transaction acting as a 32-bit master by not asserting PCI_REQ64_L on
subsequent cycle.
4. If the target responses to PCI_REQ64_L with PCI_ACK64_L de-asserted and PCI STOP_L
asserted, PCI Unit will complete the transaction by not asserting PCI_REQ64_L on
subsequent cycles.