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18 Hardware Reference Manual
Contents
98 CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Full Duplex Mode ......................... 277
99 CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Simplex Mode .............................. 278
100 MSF to Command and Push and Pull Buses Interface Block Diagram.................................... 290
101 Basic I/O Capability of the Intel® IXP2800 Network Processor................................................ 292
102 Simplex Configuration .............................................................................................................. 293
103 Hybrid Simplex Configuration ...................................................................................................294
104 Dual Network Processor, Full Duplex Configuration ................................................................ 295
105 Single Network Processor, Full Duplex Configuration (SPI-4.2 Protocol) ................................ 296
106 Single Network Processor, Full Duplex Configuration (SPI-4.2 and CSIX-L1 Protocols)......... 297
107 Framer, Single Network Processor Ingress and Egress, and Fabric Interface Chip ................ 298
108 Framer, Dual Processor Ingress, Single Processor Egress, and Fabric Interface Chip........... 298
109 Framer, Single Network Processor Ingress, Single Network Processor Egress,
CSIX-L1 Translation Chip and CSIX-L1 Fabric Interface Chip................................................. 299
110 CPU Complex, Network Processor, and Fabric Interface Chips .............................................. 299
111 Framer, Single Network Processor, Co-Processor, and Fabric Interface Chip ........................ 300
112 SPI-4.2 Interface Reference Model with Receiver and Transmitter Labels
Corresponding to Link Layer Device Functions........................................................................ 301
113 CSIX-L1 Interface Reference Model with Receiver and Transmitter Labels
Corresponding to Fabric Interface Chip Functions ................................................................... 303
114 Reference Model for IXP2800 Support of the Simplex Configuration Using
Independent Ingress and Egress Interfaces............................................................................. 306
115 Reference Model for Hybrid Simplex Operation ....................................................................... 307
116 Block Diagram of Dual Protocol (SPI-4.2 and CSIX-L1) Bridge Chip....................................... 313
117 Summary of Receiver and Transmitter Signaling ..................................................................... 317
118 PCI Functional Blocks .............................................................................................................. 320
119 Data Access Paths ................................................................................................................... 321
120 PCI Arbiter Configuration Using CFG_PCI_ARB(GPIO[2]) ...................................................... 331
121 Example of Target Write to SRAM of 68 Bytes ........................................................................ 333
122 Example of Target Write to DRAM of 68 Bytes ........................................................................ 335
123 Example of Target Read from DRAM Using 64-Byte Burst...................................................... 336
124 Generation of the Doorbell Interrupts to PCI ............................................................................ 337
125 Generation of the Doorbell Interrupts to the Intel XScale® Core.............................................. 338
126 PCI Interrupts ........................................................................................................................... 339
127 DMA Descriptor Reads............................................................................................................. 342
128 PCI Address Generation for Command Bus Master to PCI...................................................... 346
129 PCI Address Generation for Command Bus Master to PCI Configuration Cycle ..................... 347
130 Overall Clock Generation and Distribution ............................................................................... 360
131 IXP2800 Network Processor Clock Generation........................................................................ 363
132 Synchronization Between Frequency Domains........................................................................ 364
133 Reset Out Behavior .................................................................................................................. 365
134 Reset Generation ..................................................................................................................... 366
135 Boot Process ............................................................................................................................ 371
136 Performance Monitor Interface Block Diagram......................................................................... 376
137 Block Diagram of a Single CHAP Counter ............................................................................... 378
138 Basic Block Diagram of IXP2800 Network Processor with PMU.............................................. 379
139 CAP Interface to the APB ......................................................................................................... 380
140 Conceptual Diagram of Counter Array ..................................................................................... 382