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Intel
®
IXP2800 Network Processor
Performance Monitor Unit
71 XG_SRAM_WR_2_CPP P_CLK single separate XG SRAM write length=2 on cpp bus
72 XG_SRAM_WR_3_CPP P_CLK single separate XG SRAM write length=3 on cpp bus
73 XG_SRAM_WR_4_CPP P_CLK single separate XG SRAM write length=4 on cpp bus
74 XG_SRAM_CSR_RD_CPP P_CLK single separate XG SRAM csr read command on cpp bus
75 XG_SRAM_CSR_WR_CPP P_CLK single separate XG SRAM csr write command on cpp bus
76 XG_SRAM_ATOM_CPP P_CLK single separate XG SRAM atomic command on cpp bus
77 XG_SRAM_GET_CPP P_CLK single separate XG SRAM get command on cpp bus
78 XG_SRAM_PUT_CPP P_CLK single separate XG SRAM put command on cpp bus
79 XG_SRAM_ENQ_CPP P_CLK single separate XG SRAM enq command on cpp bus
80 XG_SRAM_DEQ_CPP P_CLK single separate XG SRAM deq command on cpp bus
81 XG_S0_ACC_CPP P_CLK single separate XG SRAM channel0 access on cpp bus
82 XG_S1_ACC_CPP P_CLK single separate XG SRAM channel1 access on cpp bus
83 XG_S2_ACC_CPP P_CLK single separate XG SRAM channel2 access on cpp bus
84 XG_S3_ACC_CPP P_CLK single separate XG SRAM channel3 access on cpp bus
85 XG_SCR_RD_CPP P_CLK single separate XG scratch read command on cpp bus
86 XG_SCR_RD_1_CPP P_CLK single separate XG scratch read length=1 on cpp bus
87 XG_SCR_RD_8_CPP P_CLK single separate XG scratch read length=8 on cpp bus
88 XG_SCR_WR_CPP P_CLK single separate XG scratch write command on cpp bus
89 XG_SCR_WR_1_CPP P_CLK single separate XG scratch write length=1 on cpp bus
90 XG_SCR_WR_2_CPP P_CLK single separate XG scratch write length=2 on cpp bus
91 XG_SCR_WR_3_CPP P_CLK single separate XG scratch write length=3 on cpp bus
92 XG_SCR_WR_4_CPP P_CLK single separate XG scratch write length=4 on cpp bus
93 XG_SCR_ATOM_CPP P_CLK single separate XG scratch atomic command on cpp bus
94 XG_SCR_GET_CPP P_CLK single separate XG scratch get command on cpp bus
95 XG_SCR_PUT_CPP P_CLK single separate XG scratch put command on cpp bus
96 XG_DRAM_RD_CPP P_CLK single separate XG DRAM read command on cpp bus
97 XG_DRAM_RD_1_CPP P_CLK single separate XG DRAM read length=1 on cpp bus
98 XG_DRAM_RD_4_CPP P_CLK single separate XG DRAM read length=4 on cpp bus
99 XG_DRAM_WR_CPP P_CLK single separate XG DRAM write on cpp bus
100 XG_DRAM_WR_1_CPP P_CLK single separate XG DRAM write length=1 on cpp bus
101 XG_DRAM_WR_2_CPP P_CLK single separate XG DRAM write length=2 on cpp bus
102 XG_DRAM_CSR_RD_CPP P_CLK single separate XG DRAM csr read command on cpp bus
103 XG_DRAM_CSR_WR_CPP P_CLK single separate XG DRAM csr write command on cpp bus
104 XG_MSF_RD_CPP P_CLK single separate XG msf read command on cpp bus
105 XG_MSF_RD_1_CPP P_CLK single separate XG msf read length=1 on cpp bus
106 reserved
107 XG_MSF_WR_CPP P_CLK single separate XG msf write command on cpp bus
108 XG_MSF_WR_1_CPP P_CLK single separate XG msf write length=1 on cpp bus
109 XG_MSF_WR_2_CPP P_CLK single separate XG msf write length=2 on cpp bus
Table 158. Intel XScale
®
Core Gasket PMU Event List (Sheet 3 of 4)