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Hardware Reference Manual 17
Contents
48 An Interface Topology with Intel / AMCC* SONET/SDH Device ..............................................158
49 Mode 3 Second Interface Topology with Intel / AMCC* SONET/SDH Device..........................159
50 Mode 3 Single Write Transfer Followed by Read (B0) .............................................................160
51 Mode 3 Single Read Transfer Followed by Write (B0) .............................................................161
52 An Interface Topology with Intel / AMCC* SONET/SDH Device in Motorola* Mode ................162
53 Second Interface Topology with Intel / AMCC* SONET/SDH Device.......................................163
54 Mode 4 Single Write Transfer (B0) ...........................................................................................164
55 Mode 4 Single Read Transfer (B0) ...........................................................................................165
56 Microengine Block Diagram......................................................................................................168
57 Context State Transition Diagram.............................................................................................170
58 Byte Align Block Diagram .........................................................................................................175
59 CAM Block Diagram .................................................................................................................177
60 Read from RBUF (64 Bits)........................................................................................................181
61 Write to TBUF (64 Bits).............................................................................................................182
62 48-, 64-, and 128-Bit Hash Operand Transfers ........................................................................183
63 Bit, Byte, and Longword Organization in One RBUF Element..................................................184
64 Write to TBUF ...........................................................................................................................185
65 MSF Interface ...........................................................................................................................186
66 Clock Configuration ..................................................................................................................189
67 IXP2800 Clocking for RDRAM at 400 MHz ..............................................................................190
68 IXP2800 Clocking for RDRAM at 508 MHz ..............................................................................190
69 Address Mapping Flow .............................................................................................................191
70 RDRAM Controller Block Diagram............................................................................................198
71 DRAM Push/Pull Arbiter Functional Blocks ..............................................................................202
72 DRAM Push Arbiter Functional Blocks .....................................................................................204
73 DRAM Pull Arbiter Functional Blocks .......................................................................................205
74 SRAM Controller/Chassis Block Diagram.................................................................................208
75 SRAM Clock Connection on a Channel....................................................................................210
76 External Pipeline Registers Block Diagram ..............................................................................211
77 Queue Descriptor with Four Links ............................................................................................213
78 Enqueueing One Buffer at a Time ............................................................................................213
79 Previously Linked String of Buffers...........................................................................................214
80 First Step to Enqueue a String of Buffers to a Queue (ENQ_Tail_and_Link)...........................214
81 Second Step to Enqueue a String of Buffers to a Queue (ENQ_Tail) ......................................214
82 Connection to a Coprocessor Though Standard QDR Interface ..............................................221
83 Coprocessor with Memory Mapped FIFO Ports .......................................................................222
84 SHaC Top Level Diagram.........................................................................................................226
85 Scratchpad Block Diagram .......................................................................................................228
86 Ring Communication Logic Diagram ........................................................................................231
87 Hash Unit Block Diagram..........................................................................................................236
88 Example System Block Diagram ..............................................................................................242
89 Full-Duplex Block Diagram .......................................................................................................243
90 Receive and Transmit Clock Generation ..................................................................................245
91 Simplified Receive Section Block Diagram...............................................................................247
92 RBUF Element State Diagram..................................................................................................257
93 Extent of DIP-4 Codes ..............................................................................................................260
94 Simplified Transmit Section Block Diagram..............................................................................262
95 TBUF State Diagram ................................................................................................................270
96 Tx Calendar Block Diagram......................................................................................................271
97 CSIX Flow Control Interface — TXCSRB and RXCSRB ..........................................................275