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56 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
2.5.5.2 Microengine Software Restrictions to Maintain Ordering
It is the Microengine programmer’s job to ensure order where the program flow finds order to be
necessary and where the architecture does not guarantee that order. The signaling mechanism can
be used to do this. For example, say that microcode needs to update several locations in a table. A
location in SRAM is used to “lock” access to the table. Example 13 is the code for the table update.
Other rules:
• All accesses to atomic variables should be via read-modify-write instructions.
• If the flow must know that a write is completed (actually in the SRAM itself), follow the write
with a read to the same address. The write is guaranteed to be complete when the read data has
been returned to the Microengine.
• With the exception of initialization, never do WRITE commands to the first three longwords
of a queue_descriptor data structure (these are the longwords that hold head, tail, and count,
etc.). All accesses to this data must be via the Q commands.
• To initialize the Q_array registers, perform a memory write of at least three longwords,
followed by a memory read to the same address (to guarantee that the write completed).
Then, for each entry in the Q_array, perform a read_q_descriptor_head followed by a
read_q_descriptor_other using the address of the same three longwords.
2.6 Scratchpad Memory
The IXP2800 Network Processor contains a 16 Kbytes of Scratchpad Memory, organized as 4K
32-bit words, that is accessible by Microengines and the Intel XScale
®
core. The Scratchpad
Memory provides the following operations:
• Normal reads and writes. 1–16 32-bit words can be read/written with a single Microengine
instruction. Note that Scratchpad is not byte-writable (each write must write all four bytes).
• Atomic read-modify-write operations, bit-set, bit-clear, increment, decrement, add, subtract,
and swap. The RMW operations can also optionally return the pre-modified data.
• Sixteen Hardware Assisted Rings for interprocess communication. (A ring is a FIFO that uses
a head and tail pointer to store/read information in Scratchpad memory.)
Scratchpad Memory is provided as a third memory resource (in addition to SRAM and DRAM)
that is shared by the Microengines and the Intel XScale
®
core. The Microengines and the Intel
XScale
®
core can distribute memory accesses between these three types of memory resources to
provide a greater number of memory accesses occurring in parallel.
Example 13. Table Update Code
IMMED [$xfer0, 1]
SRAM [write, $xfer0, flag_address, 0, 1], ctx_swap [SIG_DONE_2]
; At this point, the write to flag_address has passed the point of coherency. Do
the table updates.
SRAM [write, $xfer1, table_base, offset1, 2] , sig_done [SIG_DONE_3]
SRAM [write, $xfer3, table_base, offset2, 2] , sig_done [SIG_DONE_4]
CTX_ARB [SIG_DONE_3, SIG_DONE_4]
; At this point, the table writes have passed the point of coherency. Clear the
flag to allow access by other threads.
IMMED [$xfer0, 0]
SRAM [write, $xfer0, flag_address, 0, 1, ctx_swap [SIG_DONE_2]