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428 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
57 reserved
58 reserved
59 deq_split_cmd_fifo_wph P_CLK single separate Active when dequeueing from the split inlet FIFO.
60 deq_inlet_fifo1_wph P_CLK single separate Active when dequeueing from the inlet FIFO.
61 deq_inlet_fifo_wph P_CLK single separate
Active when dequeueing from either the inlet or
split-inlet FIFO.
62
DCB_PULL_CTRL_AVAL_W
PH
P_CLK single separate Indicates the pull control FIFO has >= 1 entry.
63 inlet_cmd_aval_rph P_CLK single separate
Indicates a command is available in the non-split
inlet FIFO.
64 split_fifo_not_empty P_CLK single separate
Indicates a command is available in the ”split
inlet” FIFO (split refers to a command being split
across channels).
65 bank3_pull_ok_wph P_CLK single separate
Indicates that this bank's data FIFO has enough
room to accommodate the size of the next pull
command in the inlet FIFO.
66 bank2_pull_ok_wph P_CLK single separate
Indicates that this bank's data FIFO has enough
room to accommodate the size of the next pull
command in the inlet FIFO.
67 bank1_pull_ok_wph P_CLK single separate
Indicates that this bank's data FIFO has enough
room to accommodate the size of the next pull
command in the inlet FIFO.
68 bank0_pull_ok_wph P_CLK single separate
Indicates that this bank's data FIFO has enough
room to accommodate the size of the next pull
command in the inlet FIFO.
69 csr_q_full_wph P_CLK single separate Indicates that a CSR access is in process.
70 DXDP_CMD_Q_FULL_RPH P_CLK single separate
Indicates the command inlet FIFO contains > 8
entries.
71 pull_ctrl_fifo_full P_CLK single separate
Indicates that there are > 6 outstanding pull
requests.
72 bank3_cmd_q_full_rph P_CLK single separate
Indicates the bank command FIFO contains > 6
entries.
73 bank2_cmd_q_full_rph P_CLK single separate
Indicates the bank command FIFO contains > 6
entries.
74 bank1_cmd_q_full_rph P_CLK single separate
Indicates the bank command FIFO contains > 6
entries.
75 bank0_cmd_q_full_rph P_CLK single separate
Indicates the bank command FIFO contains > 6
entries.
76 valid_write_req_wph P_CLK single separate
Indicates a DRAM write is being passed from the
inlet FIFO to a bank FIFO. The DRAM write may
be: DRAM RBUF read, DRAM write, or CSR
write.
77 csr_q_full_en_wph P_CLK single separate
Pulses at both the start of a CSR read/write and
at the completion of a CSR read/write.
78 push_rmw_wr_cmd_wph P_CLK single separate
Indicates the command being passed from the
inlet FIFO to a bank FIFO is a read-modify-write.
79 bank3_enq_wph P_CLK single separate
Indicates this channel is enqueueing a DRAM
command for bank3.
Table 184. IXP2800 Network Processor Dram CH2 PMU Event List (Sheet 4 of 5)