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Hardware Reference Manual 273
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.3.4.2 CSIX
There are two types of CSIX flow control:
• Link-level
• Virtual Output Queue (VOQ)
8.3.4.2.1 Link-Level
The Link-level flow control function is done via hardware and consists of two parts:
1. Enable/disable transmission of valid TBUF elements.
2. Ready field to be sent in CFrames sent to the Switch Fabric.
As described in Section 8.2.7, the Ready Field of received CFrames is placed into
FC_Egress_Status[SF_CReady] and FC_Egress_Status[SF_DReady]. The value in those bits is
sent to the Ingress IXP2800 Network Processor on TXCSRB. In Full Duplex Mode, the
information is received on RXCSRB by the Ingress IXP2800 Network Processor and put into
FC_Ingress_Status[SF_CReady] and FC_Ingress_Status[SF_DReady]. Those bits allow or
stop transmission of Control and Data elements, respectively. When one of those bits transitions
from allowing transmission to stopping transmission, the current CFrame in progress (if any) is
completed, and the next CFrame of that type is prevented from starting.
As described in Section 8.2.7, if the Egress IXP2800 Network Processor RBUF gets near full, or if
the Egress IXP2800 Network Processor FCEFIFO gets near full, it will send that information on
TXCSRB. Those bits are put into FC_Ingress_Status[TM_CReady] and
FC_Ingress_Status[TM_DReady], and are used as the value in CFrame Base Header Control
Ready and Data Ready, respectively.
8.3.4.2.2 Virtual Output Queue
The Virtual Output Queue flow control function is done by software, with hardware support.
As described in Section 8.2.7, the CSIX Flow Control CFrames received on the Egress IXP2800
Network Processor are passed to the Ingress IXP2800 Network Processor over TXCDAT. The
information is received on RXCDAT and placed into the FCIFIFO. A Microengine reads that
information by
msf[read], and uses it to maintain per-VOQ information. The way in which that
information is used is application-dependent and is done in software. The hardware mechanism is
described in Section 8.5.3.
8.3.5 Parity
8.3.5.1 SPI-4
DIP-4 parity is computed by Transmit hardware placed into the Control Word sent at the beginning
of transmission of a TBUF element, and also on Idle Control Words sent when no TBUF element is
valid. The value to place into the DIP-4 field is computed on the preceding Data Words (if any),
and the current Control Word.