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196 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
DRAM
To avoid the detection of false ECC errors, the RDRAM ECC mode must be initialized using the
procedure described below:
1. Ensure that parity/ECC is not enabled: program DRAM_CTRL[15:14] = 00
2. Write all zeros (0x00000000) to all the memory locations. By default, this initializes the
memory with odd parity and in this case (data all 0), it coincides with ECC and does not
require any read-modify-writes because ECC is not enabled.
3. Ensure that all of the writes are completed prior to enabling ECC. This is done by performing
a read operation to 1000 locations.
4. Enable ECC mode: program DRAM_CTRL[15:14] accordingly.
5.6.4 ECC Calculation and Syndrome
The ECC check bits are calculated by forming parity checks on groups of data bits. The check bits
are stored in memory during writes via the dqa[8] and dqb[8] signals. Note that memory
initialization code must put good ECC into all of memory by writing each location before it can be
read. Writing any arbitrary data into memory – for example 0, will accomplish this. This will take
several milliseconds per Mbyte of memory.
On reads, the expected code is calculated from the data, and then compared to (XORed) the ECC
that was read. The result of the comparison is called the syndrome. If the syndrome is equal to 0,
then there was no error. There are eight syndromes that are calculated based on the read data and its
corresponding ECC bit. When ECC is enabled, upon detecting a single-bit error, the syndrome is
used to determine which bit needs to be flipped to correct the error.
5.7 Timing Configuration
Table 66 shows the example timing settings for RDRAMs of various speeds. The parameters are
programmed in the RDRAM_Config CSRs (refer to the PRM for register descriptions)
.
Table 66. RDRAM Timing Parameter Settings
Parameter
Name
-40-
800
-45-
800
-50-
800
-45-
711
-50-
711
-45-
600
-53-
600
CfgTrcd 79117957
CfgTrasSyn5565545
CfgTrp 88108868
CfgToffpSyn4444444
CfgTrasrefSyn5565545
CfgTprefSyn2222222