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Hardware Reference Manual 319
Intel
®
IXP2800 Network Processor
PCI Unit
PCI Unit 9
This section contains information on the IXP2800 Network Processor PCI Unit.
9.1 Overview
The PCI Unit allows PCI target transactions to internal registers, SRAM, and DRAM. It also
generates PCI initiator transactions from the DMA Engine, Intel XScale
®
core, and Microengines.
The PCI Unit main functional blocks are shown in Figure 118 and include:
• PCI Core Logic
• PCI Bus Arbiter
• DRAM Interface Logic
• SRAM Interface Logic
• Mailbox and Message registers
• DMA Engine
• Intel XScale
®
core Direct Access to PCI
The main function of the PCI Unit is to transfer data between the PCI Bus and the internal devices,
which are the Intel XScale
®
core, the internal registers, and memories.
These are the data transfer paths supported as shown in Figure 119:
• PCI Slave read and write between PCI and internal buses
— CSRs (PCI_CSR_BAR)
— SRAM (PCI_SRAM_BAR)
— DRAM (PCI_DRAM_BAR)
• Push/Pull Master (Intel XScale
®
core, Microengine, or PCI) accesses to internal registers
within PCI unit
• DMA
— Descriptor read from SRAM
— Data transfers between PCI and DRAM
• Push/Pull Master (Intel XScale
®
core and Microengines) direct read and write to PCI Bus
Note: Detailed information about CSRs is contained in the Intel
®
IXP2400 and IXP2800 Network
Processor Programmer’s Reference Manual.