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Hardware Reference Manual 187
Intel
®
IXP2800 Network Processor
DRAM
DRAM 5
This section describes Rambus* DRAM operation.
5.1 Overview
The IXP2800 Network Processor has controllers for three Rambus* DRAM (RDRAM) channels.
Either one, two, or three channels can be enabled. When more than one channel is enabled, the
channels are interleaved (also known as striping) on 128-byte boundaries to provide balanced
access to all populated channels. Interleaving is performed in hardware and is transparent to the
programmer. The programmer views the DRAM memory space as a contiguous block of memory.
The total address space of two Gbytes is supported by the DRAM interface regardless of the
number of channels that are enabled. The controllers support 64-, 128-, 256-, and 512-Mbyte, and
1-Gbyte devices; however, with interleaving, each of the channels must have the same number,
size, and speed of RDRAMs populated. Each channel can be populated with up to 32 RDRAM
devices. While each channel must have the same size and speed RDRAMs, it is possible for each
individual channel to have different size and speed RDRAMs, as long as the total amount of
memory is the same for all of the channels.
ECC (Error Correcting Code) is supported. Enabling ECC requires that x18 RDRAMs be used.
If ECC is disabled, x16 RDRAMs can be used.
The Microengines (MEs), Intel XScale
®
core, and PCI (external Bus Masters and DMA Channels)
have access to the DRAM memory space.
The controllers also automatically perform refresh as well as IO driver calibration to account for
variations in operating conditions due to process, temperature, voltage, and board layout.
RDRAM Powerdown and nap modes are not supported.