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6 Hardware Reference Manual
Contents
3.6.2.3.4 Write-Back versus Write-Through........................................ 101
3.6.2.4 Round-Robin Replacement Algorithm ................................................. 102
3.6.2.5 Parity Protection................................................................................... 102
3.6.2.6 Atomic Accesses.................................................................................. 102
3.6.3 Data Cache and Mini-Data Cache Control .......................................................... 103
3.6.3.1 Data Memory State After Reset ........................................................... 103
3.6.3.2 Enabling/Disabling ............................................................................... 103
3.6.3.3 Invalidate and Clean Operations.......................................................... 103
3.6.3.3.1 Global Clean and Invalidate Operation ................................ 104
3.6.4 Reconfiguring the Data Cache as Data RAM ...................................................... 105
3.6.5 Write Buffer/Fill Buffer Operation and Control ..................................................... 106
3.7 Configuration .................................................................................................................... 106
3.8 Performance Monitoring ................................................................................................... 107
3.8.1 Performance Monitoring Events .......................................................................... 107
3.8.1.1 Instruction Cache Efficiency Mode....................................................... 108
3.8.1.2 Data Cache Efficiency Mode................................................................ 109
3.8.1.3 Instruction Fetch Latency Mode........................................................... 109
3.8.1.4 Data/Bus Request Buffer Full Mode .................................................... 109
3.8.1.5 Stall/Writeback Statistics...................................................................... 110
3.8.1.6 Instruction TLB Efficiency Mode .......................................................... 111
3.8.1.7 Data TLB Efficiency Mode ................................................................... 111
3.8.2 Multiple Performance Monitoring Run Statistics .................................................. 111
3.9 Performance Considerations ............................................................................................ 111
3.9.1 Interrupt Latency.................................................................................................. 112
3.9.2 Branch Prediction ................................................................................................ 112
3.9.3 Addressing Modes ............................................................................................... 113
3.9.4 Instruction Latencies............................................................................................ 113
3.9.4.1 Performance Terms ............................................................................. 113
3.9.4.2 Branch Instruction Timings .................................................................. 115
3.9.4.3 Data Processing Instruction Timings ................................................... 115
3.9.4.4 Multiply Instruction Timings.................................................................. 116
3.9.4.5 Saturated Arithmetic Instructions ......................................................... 117
3.9.4.6 Status Register Access Instructions .................................................... 118
3.9.4.7 Load/Store Instructions ........................................................................ 118
3.9.4.8 Semaphore Instructions ....................................................................... 118
3.9.4.9 Coprocessor Instructions ..................................................................... 119
3.9.4.10 Miscellaneous Instruction Timing......................................................... 119
3.9.4.11 Thumb Instructions .............................................................................. 119
3.10 Test Features.................................................................................................................... 119
3.10.1 IXP2800 Network Processor Endianness............................................................ 120
3.10.1.1 Read and Write Transactions Initiated by the Intel XScale
®
Core ...... 121
3.10.1.1.1 Reads Initiated by the Intel XScale® Core ........................ 121
3.10.1.1.2 The Intel XScale
®
Core Writing to the IXP2800
Network Processor .................................................................. 123
3.11 Intel XScale® Core Gasket Unit ....................................................................................... 125
3.11.1 Overview.............................................................................................................. 125
3.11.2 Intel XScale® Core Gasket Functional Description ............................................. 127
3.11.2.1 Command Memory Bus to Command Push/Pull Conversion .............. 127
3.11.3 CAM Operation .................................................................................................... 127
3.11.4 Atomic Operations ............................................................................................... 128
3.11.4.1 Summary of Rules for the Atomic Command Regarding I/O ............... 129
3.11.4.2 Intel XScale® Core Access to SRAM Q-Array..................................... 129