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Hardware Reference Manual 217
Intel
®
IXP2800 Network Processor
SRAM Interface
6.4.3.3 ENQ and DEQ Commands
These commands add or remove elements from the queue structure while updating the Q_array
registers. Refer to the sections, “SRAM (Enqueue)” and “SRAM (Dequeue)”, in the IXP2400 and
IXP2800 Network Processor Programmer’s Reference Manual, for more information.
6.4.4 Ring Data Structure Commands
The ring structure commands use the Q_array registers to hold the head tail and count data for a
ring data structure, which is a fixed-size array of data with insert and remove pointers. Refer to the
section, “SRAM (Ring Operations)” in the IXP2400 and IXP2800 Network Processor
Programmer’s Reference Manual, for more information.
6.4.5 Journaling Commands
Journaling commands use the Q_array registers to index into an array of memory in the QDR
SRAM that will be periodically written with information to help debug applications running on the
IXP2400 and IXP2800 processors. Once the array has been completely written once, subsequent
journal writes overwrite the previously written data — only the most recent data will be present in
the data structure. Refer to the section, “SRAM (Journal Operations)”, in the IXP2400 and
IXP2800 Network Processor Programmer’s Reference Manual, for more information.
6.4.6 CSR Accesses
CSR accesses will write or read CSRs within each controller. The upper address bits will determine
which channel will respond, while the CSR address within a channel are given in the lower address
bits.
6.5 Parity
SRAM can be optionally protected by byte parity. Even parity is used — the combination of eight
data bits and the corresponding parity bit will have an even number of ‘1s’. The SRAM controller
generates parity on all SRAM writes. When parity is enabled (
SRAM_Control[Par_Enable]),
the SRAM controller checks for correct parity on all reads.
Upon detection of a parity error on a read, or the read portion of an atomic read-modify-write, the
SRAM controller records the address of the location with bad parity in
SRAM_Parity[Address]
and sets the appropriate
SRAM_Parity[Error] bit(s). Those bit(s) interrupt the Intel XScale
®
core when enabled in IRQ_Enable[SRAM_Parity] or FIQ_Enable[SRAM_Parity].
The Data Error signal in the
Push_CMD is asserted when the data to be read is delivered (unless the
token
Ignore Data Error was asserted in the command; in that case, the SRAM controller does
not assert Data Error). When Data Error is asserted, the Push Arbiter suppresses the Microengine
signal if the read was originated by a Microengine (it uses
0x0, which is a null signal, in place of
the requested signal number).