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322 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
If a read address is latched, the subsequent cycles will be retried and no address will be latched
until the read completes. The initiator address FIFO can accumulate up to four addresses that can
be PCI reads or writes.
These FIFOs are inside the PCI Core, which stores data received from the PCI Bus or data to be
sent out to the PCI Bus. There are additional buffers implemented in other sub-blocks that buffers
data to and from the internal push/pull buses.
Table 118 lists the maximum PCI Interface loading.
9.2.1 PCI Commands
Table 119 lists the supported PCI commands and identifies them as either a target or initiator.
Table 117. PCI Block FIFO Sizes
Location Depth
Target Address 4
Target Write Data 8
Target Read Data 8
Initiator Address 4
Initiator Write Data 8
Initiator Read Data 8
Table 118. Maximum Loading
Bus Interface Maximum Number of Loads Trace Length (inches)
PCI
Four loads at 66-MHz bus frequency
Eight loads at 33-MHz bus frequency
5 to 7
Table 119. PCI Commands (Sheet 1 of 2)
C_BE_L Command
Support
Target Initiator
0x0 Interrupt Acknowledge Not Supported Supported
0x1 Special Cycle Not Supported Supported
0x2 IO Read cycle Not Supported Supported
0x3 IO Write cycle Not Supported Supported
0x4 Reserved – –
0x5 Reserved – –
0x6 Memory Read Supported Supported
0x7 Memory Write Supported Supported
0x8 Reserved – –
0x9 Reserved – –
0xA Configuration Read Supported Supported
0xB Configuration Write Supported Supported