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8 Hardware Reference Manual
Contents
4.3.1 Byte Align............................................................................................................. 174
4.3.2 CAM..................................................................................................................... 176
4.4 CRC Unit...........................................................................................................................179
4.5 Event Signals.................................................................................................................... 180
4.5.1 Microengine Endianness ..................................................................................... 181
4.5.1.1 Read from RBUF (64 Bits)................................................................... 181
4.5.1.2 Write to TBUF ...................................................................................... 182
4.5.1.3 Read/Write from/to SRAM ................................................................... 182
4.5.1.4 Read/Write from/to DRAM ................................................................... 182
4.5.1.5 Read/Write from/to SHaC and Other CSRs......................................... 182
4.5.1.6 Write to Hash Unit................................................................................ 183
4.5.2 Media Access ......................................................................................................183
4.5.2.1 Read from RBUF ................................................................................. 184
4.5.2.2 Write to TBUF ...................................................................................... 185
4.5.2.3 TBUF to SPI-4 Transfer ....................................................................... 186
5 DRAM.......................................................................................................................................... 187
5.1 Overview........................................................................................................................... 187
5.2 Size Configuration ............................................................................................................188
5.3 DRAM Clocking ................................................................................................................189
5.4 Bank Policy....................................................................................................................... 190
5.5 Interleaving ....................................................................................................................... 191
5.5.1 Three Channels Active (3-Way Interleave).......................................................... 191
5.5.2 Two Channels Active (2-Way Interleave) ............................................................ 193
5.5.3 One Channel Active (No Interleave) .................................................................... 193
5.5.4 Interleaving Across RDRAMs and Banks ............................................................194
5.6 Parity and ECC................................................................................................................. 194
5.6.1 Parity and ECC Disabled ..................................................................................... 194
5.6.2 Parity Enabled ..................................................................................................... 195
5.6.3 ECC Enabled ....................................................................................................... 195
5.6.4 ECC Calculation and Syndrome .......................................................................... 196
5.7 Timing Configuration.........................................................................................................196
5.8 Microengine Signals .........................................................................................................197
5.9 Serial Port.........................................................................................................................197
5.10 RDRAM Controller Block Diagram.................................................................................... 198
5.10.1 Commands .......................................................................................................... 199
5.10.2 DRAM Write......................................................................................................... 199
5.10.2.1 Masked Write....................................................................................... 199
5.10.3 DRAM Read......................................................................................................... 200
5.10.4 CSR Write............................................................................................................ 200
5.10.5 CSR Read............................................................................................................ 200
5.10.6 Arbitration ............................................................................................................ 201
5.10.7 Reference Ordering ............................................................................................. 201
5.11 DRAM Push/Pull Arbiter ................................................................................................... 201
5.11.1 Arbiter Push/Pull Operation ................................................................................. 202
5.11.2 DRAM Push Arbiter Description .......................................................................... 203
5.12 DRAM Pull Arbiter Description.......................................................................................... 204
6 SRAM Interface.......................................................................................................................... 207
6.1 Overview........................................................................................................................... 207
6.2 SRAM Interface Configurations ........................................................................................ 208