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Hardware Reference Manual 313
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.9.5.3 Implementation of a Bridge Chip to CSIX-L1 and SPI-4.2
A bridge chip can provide support for both standard CSIX-L1 and standard physical layer device
interfaces such as SPI-3 or UTOPIA Level 3. The bridge chip must implement the functionality of
the less trivial CSIX-L1 bridge chip described previously and additionally, implement bridge
functionality between SPI-4.2 and the other physical device interfaces. The size of the FIFOs must
be in accordance with the response times of the flow control mechanisms. Figure 116 is a block
diagram of a dual protocol (SPI-4.2 and CSIX-L1) bridge chip.
Figure 116. Block Diagram of Dual Protocol (SPI-4.2 and CSIX-L1) Bridge Chip
B2754-01
Data
Control
DE-MUX
ARB
SPI
Data
Control
CSIX-L1
SPI/
UTOPIA-3
Dual-Protocol
Intel
®
IXP2800 Network Processor Interface
SPI/
UTOPIA-3
SPI/
UTOPIA-3
DE-MUX
SPI
ARBDE-MUXARB